Distributed quantum error correction for chip-level catastrophic errors

Abstract

Quantum error correction holds the key to scaling up quantum computers. Cosmic ray events severely impact the operation of a quantum computer by causing chip-level catastrophic errors, essentially erasing the information encoded in a chip. Here, we present a distributed error correction scheme to combat the devastating effect of such events by introducing an additional layer of quantum erasure error correcting code across separate chips. We show that our scheme is fault tolerant against chip-level catastrophic errors and discuss its experimental implementation using superconducting qubits with microwave links. Our analysis shows that in state-of-the-art experiments, it is possible to suppress the rate of these errors from 1 per 10 seconds to less than 1 per month.

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• Modeling phonon-mediated quasiparticle poisoning in superconducting qubit arrays
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• Cosmic-ray-induced correlated errors in superconducting qubit array
• Hierarchical memories: Simulating quantum LDPC codes with local gates
• Long-Range $ZZ$ Interaction via Resonator-Induced Phase in Superconducting Qubits
• Distributed multi-parameter quantum metrology with a superconducting quantum network
• Nonequilibrium regimes for quasiparticles in superconducting qubits with gap-asymmetric junctions
• Fight or Flight: Cosmic Ray-Induced Phonons and the Quantum Surface Code
• Averting multi-qubit burst errors in surface code magic state factories
• First Measurement of Correlated Charge Noise in Superconducting Qubits at an Underground Facility
• Mitigating cosmic ray-like correlated events with a modular quantum processor
• Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors
• Network Requirements for Distributed Quantum Computation