Contact resistance extraction of graphene FET technologies based on individual device characterization

Abstract

Straightforward contact resistance extraction methods based on electrical device characteristics are described and applied here to graphene field-effect transistors from different technologies. The methods are an educated adaptation of extraction procedures originally developed for conventional transistors by exploiting the drift-diffusion-like transport in graphene devices under certain bias conditions. In contrast to other available approaches for contact resistance extraction of graphene transistors, the practical methods used here do not require either the fabrication of dedicated test structures or internal device phenomena characterization. The methodologies are evaluated with simulation-based data and applied to fabricated devices. The extracted values are close to the ones obtained with other more intricate methodologies. Bias-dependent contact and channel resistances studies, bias-dependent high-frequency performance studies and contact engineering studies are enhanced and evaluated by the extracted contact resistance values.

References in corpus (6)

• Mobility and Saturation Velocity in Graphene on SiO2
• Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors
• Short channel effects in graphene-based field effect transistors targeting radio-frequency applications
• Large Scale Integration of Graphene Transistors for Potential Applications in the Back End of the Line
• The role of the Fermi level pinning in gate tunable graphene-semiconductor junctions
• Accuracy of Y-function methods for parameters extraction of two-dimensional FETs across different technologies

Cited by in corpus (2)

• Compact modeling technology for the simulation of integrated circuits based on graphene field-effect transistors
• Accuracy of Y-function methods for parameters extraction of two-dimensional FETs across different technologies