Charge trap layer enabled positive tunable V$_{fb}$ in $β$-Ga$_{2}$O$_{3}$ gate stacks for enhancement mode transistors

Dipankar Biswas; Chandan Joishi; Jayeeta Biswas; Prabhans Tiwari; Saurabh Lodha

doi:10.1063/5.0014813

paper

Charge trap layer enabled positive tunable V $_{f b}$ in $β$ -Ga $_{2}$ O $_{3}$ gate stacks for enhancement mode transistors

arXiv:2005.05237 · doi:10.1063/5.0014813

Abstract

$β$ -Ga $_{2}$ O $_{3}$ based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A novel approach towards attaining a high positive flat band voltage (V $_{f b}$ ) of 10.6 V in $β$ -Ga $_{2}$ O $_{3}$ metal-oxide-semiconductor capacitors (MOSCAPs), with the ability to fine tune it between 3.5 V to 10.6 V, using a polycrystalline AlN charge trap layer has been demonstrated. This can enable enhancement mode operation over a wide doping range. Excellent V $_{f b}$ retention of $\sim$ 97% for 10 $^{4}$ s at 55 $^{\circ}$ C was exhibited by the gate stacks after charge trapping, hence reducing the requirement of frequent charge injection cycles. In addition, low gate leakage current density (J $_{g}$ ) for high negative gate voltages (V $_{g}$ $\sim$ -60 V) indicates the potential of this gate stack to enable superior breakdown characteristics in enhancement mode transistors.

Single file (Manuscript and Supplementary material combined) of 19 pages. Total 5 and 4 figures in manuscript and supplementary material, respectively

Charge trap layer enabled positive tunable Vfb​ in β-Ga2​O3​ gate stacks for enhancement mode transistors

Abstract

Charge trap layer enabled positive tunable V $_{f b}$ in $β$ -Ga $_{2}$ O $_{3}$ gate stacks for enhancement mode transistors