Studies of irradiated AMS H35 CMOS detectors for the ATLAS tracker upgrade

Abstract

Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area ($18.49\times 24.40\mathrm{m}{\mathrm{m}}^2$) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structures from chips with different substrate resistivity are shown for non irradiated and irradiated devices up to a cumulative fluence of $2\cdot 10^{15}1\mathrm{MeV}{\mathrm{n}}_{\mathrm{eq}}/c{\mathrm{m}}^2$.

Cited by in corpus (10)

• Technical design of the phase I Mu3e experiment
• Charge collection properties of irradiated depleted CMOS pixel test structures
• Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process
• Performance of CMOS pixel sensor prototypes in ams H35 and aH18 technology for the ATLAS ITk upgrade
• Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments
• Charge collection characterisation with the Transient Current Technique of the ams H35DEMO CMOS detector after proton irradiation
• Investigation of the Boron removal effect induced by 5.5 MeV electrons on highly doped EPI- and Cz-silicon
• Characterisation of analogue front end and time walk in CMOS active pixel sensor
• Study of neutron irradiation effects in Depleted CMOS detector structures
• Characterisation of AMS H35 HV-CMOS monolithic active pixel sensor prototypes for HEP applications