A 237 Gbps Unrolled Hardware Polar Decoder

Abstract

In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput of over 237 Gbps for a (1024,512) polar code implemented using an FPGA. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.

4 pages, 3 figures

References in corpus (3)

• Channel polarization: A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels
• Fast Polar Decoders: Algorithm and Implementation
• Scalable Successive-Cancellation Hardware Decoder for Polar Codes

Cited by in corpus (7)

• Multi-mode Unrolled Architectures for Polar Decoders
• Hardware Decoders for Polar Codes: An Overview
• A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code
• Polar Codes-based Information Reconciliation Scheme with Frozen Bits Erasure Strategy for Quantum Key Distribution
• A Constituent Codes Oriented Code Construction Scheme for Polar Code-Aim to Reduce the Decoding Latency
• Fast Encoding and Decoding of Flexible-Rate and Flexible-Length Polar Codes
• Fast Block Sequential Decoding of Polar Codes