Scalable Successive-Cancellation Hardware Decoder for Polar Codes

Abstract

Polar codes, discovered by Arıkan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existing capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.

References in corpus (2)

• Fast Polar Decoders: Algorithm and Implementation
• Hardware Architecture for List SC Decoding of Polar Codes

Cited by in corpus (12)

• Improved Successive Cancellation Flip Decoding of Polar Codes Based on Error Distribution
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• Polar Codes and Their Quantum-Domain Counterparts
• A 237 Gbps Unrolled Hardware Polar Decoder
• Low-latency List Decoding Of Polar Codes With Double Thresholding
• Multi-mode Unrolled Architectures for Polar Decoders
• Fast Software Polar Decoders
• A High-Throughput Energy-Efficient Implementation of Successive-Cancellation Decoder for Polar Codes Using Combinational Logic
• Low-Latency Successive-Cancellation List Decoders for Polar Codes with Multi-bit Decision
• A multi-mode area-efficient SCL polar decoder
• Channel capacity of polar coding with a given polar mismatched successive cancellation decoder