activity
20172021
most citedRevamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution

7 citations · 15 across the 8 of their papers we have counts for

collaborators

11 papers

cs.AR20217 cited

Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution

Jie Zhang, Miryeong Kwon, Donghyun Gouk +4

Large persistent memories such as NVDIMM have been perceived as a disruptive memory technology, because they can maintain the state of a system even after a power failure and allow…

cs.OS2020

FastDrain: Removing Page Victimization Overheads in NVMe Storage Stack

Jie Zhang, Miryeong Kwon, Sanghyun Han +3

Host-side page victimizations can easily overflow the SSD internal buffer, which interferes I/O services of diverse user applications thereby degrading user-level experiences. To a…

cs.AR2020

ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis

Jie Zhang, Myoungsoo Jung

We propose ZnG, a new GPU-SSD integrated architecture, which can maximize the memory capacity in a GPU and address performance penalties imposed by an SSD. Specifically, ZnG replac…

cs.OS2019

Faster than Flash: An In-Depth Study of System Challenges for Emerging Ultra-Low Latency SSDs

Sungjoon Koh, Junhyeok Jang, Changrim Lee +3

Emerging storage systems with new flash exhibit ultra-low latency (ULL) that can address performance disparities between DRAM and conventional solid state drives (SSDs) in the memo…

cs.DC20196 cited

Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters

Sungjoon Koh, Jie Zhang, Miryeong Kwon +4

Large-scale systems with all-flash arrays have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solom…

cs.AR20191 cited

FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads

Jie Zhang, Myoungsoo Jung, Mahmut Taylan Kandemir

In this work, we propose FUSE, a novel GPU cache system that integrates spin-transfer torque magnetic random-access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize…