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cs.AI2026
LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
Shu Gu, Matthew Youngman, Yuqin Zhao +5
Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates…
cs.AI2026
AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing
Yijia Hao, Pratibha Verma, Dongxu Guo +4
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled techno…