13 citations · 41 across the 30 of their papers we have counts for
33 papers
LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
Shu Gu, Matthew Youngman, Yuqin Zhao +5
Post-route FPGA timing closure remains expert-dependent and computationally expensive. We present LATCH (LLM-Assisted Timing Closure Harness), a two-layer framework that separates…
AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing
Yijia Hao, Pratibha Verma, Dongxu Guo +4
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled techno…
A relational fabrication-to-modeling database for memristor devices
Lai Gan, Guoyang Huang, Deepika Yadav +3
Resistive random access memory (RRAM) devices, also known as memristors, are highly dependent on fabrication, location on the wafer, and measurement protocols. However, openly avai…
Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems
Mary Kong, Yuqin Zhao, Semih Vazgecen +2
FPGA-GPP heterogeneous systems combine software flexibility with the performance and energy efficiency of reconfigurable hardware. However, determining which application tasks shou…
Vision-centric generative AI models: A software-hardware perspective
Eleni Tselepi, Cristian Sestito, Shady Agwa +1
Vision generative artificial intelligence (AI) has emerged as one of the most rapidly advancing areas of deep learning. The explosion of multimodal models has made them widely asso…
LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration
Matthew Youngman, Cristian Sestito, Themis Prodromakis
Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verifica…
Parallel Spatial Photonic Programming of Optoelectronic IGZO RRAM with a compact LED Array
Andrew Adair, Joshua Robertson, Andreas Tsiamis +6
Optoelectronic resistive random-access memory elements (ORRAM) are critical emerging devices that leverage photonic technologies to bring the advantages of optical programming to t…
D-Legion: A Scalable Many-Core Architecture for Accelerating Matrix Multiplication in Quantized LLMs
Ahmed J. Abdelmaksoud, Cristian Sestito, Shiwei Wang +1
The performance gains obtained by large language models (LLMs) are closely linked to their substantial computational and memory requirements. Quantized LLMs offer significant advan…
A flexible language model-assisted electronic design automation framework
Cristian Sestito, Panagiota Kontou, Pratibha Verma +5
Large language models (LLMs) are transforming electronic design automation (EDA) by enhancing design stages such as schematic design, simulation, netlist synthesis, and place-and-r…
A Rapid-prototyping CMOS-RRAM Integration Strategy
Andreas Tsiamis, Spyros Stathopoulos, Themis Prodromakis
Moore's law has long served the semiconductor industry as the driving force for producing ever-advancing electronics technologies. However, given the economic implications and tech…
Multibit Ferroelectric Memcapacitor for Non-volatile Analogue Memory and Reconfigurable Filtering
Deepika Yadav, Spyros Stathopoulos, Patrick Foster +4
Tuneable capacitors are vital for adaptive and reconfigurable electronics, yet existing approaches require continuous bias or mechanical actuation. Here we demonstrate a voltage-pr…
DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format
Shady Agwa, Yikang Shen, Shiwei Wang +1
Nowadays, we are witnessing an Artificial Intelligence revolution that dominates the technology landscape in various application domains, such as healthcare, robotics, automotive,…
OISMA: On-the-fly In-memory Stochastic Multiplication Architecture for Matrix-Multiplication Workloads
Shady Agwa, Yihan Pan, Georgios Papandroulidakis +1
Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computa…
Adiabatic Capacitive Neuron: An Energy-Efficient Functional Unit for Artificial Neural Networks
Sachin Maheshwari, Mike Smart, Himadri Singh Raghav +2
This paper introduces a new, highly energy-efficient, Adiabatic Capacitive Neuron (ACN) hardware implementation of an Artificial Neuron (AN) with improved functionality, accuracy,…
3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads
Cristian Sestito, Ahmed J. Abdelmaksoud, Shady Agwa +1
The Von Neumann bottleneck, which relates to the energy cost of moving data from memory to on-chip core and vice versa, is a serious challenge in state-of-the-art AI architectures,…
A Hybrid Edge Classifier: Combining TinyML-Optimised CNN with RRAM-CMOS ACAM for Energy-Efficient Inference
Kieran Woodward, Eiman Kanjo, Georgios Papandroulidakis +2
In recent years, the development of smart edge computing systems to process information locally is on the rise. Many near-sensor machine learning (ML) approaches have been implemen…
L-Sort: On-chip Spike Sorting with Efficient Median-of-Median Detection and Localization-based Clustering
Yuntao Han, Yihan Pan, Xiongfei Jiang +4
Spike sorting is a critical process for decoding large-scale neural activity from extracellular recordings. The advancement of neural probes facilitates the recording of a high num…
DiP: A Scalable, Energy-Efficient Systolic Array for Matrix Multiplication Acceleration
Ahmed J. Abdelmaksoud, Shady Agwa, Themis Prodromakis
Transformers are gaining increasing attention across Natural Language Processing (NLP) application domains due to their outstanding accuracy. However, these data-intensive models a…
A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge
Georgios Papandroulidakis, Shady Agwa, Ahmet Cirakoglu +1
The continuous shift of computational bottlenecks to the memory access and data transfer, especially for AI applications, poses the urgent needs of re-engineering the computer arch…
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Architecture and Hardware Implementation
Cristian Sestito, Shady Agwa, Themis Prodromakis
Modern hardware architectures for Convolutional Neural Networks (CNNs), other than targeting high performance, aim at dissipating limited energy. Reducing the data movement cost be…
TrIM, Triangular Input Movement Systolic Array for Convolutional Neural Networks: Dataflow and Analytical Modelling
Cristian Sestito, Shady Agwa, Themis Prodromakis
In order to follow the ever-growing computational complexity and data intensity of state-of-the-art AI models, new computing paradigms are being proposed. These paradigms aim at ac…
An Energy-efficient Capacitive-RRAM Content Addressable Memory
Yihan Pan, Adrian Wheeldon, Mohammed Mughal +3
Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density…
An RRAM-Based Implementation of a Template Matching Circuit for Low-Power Analogue Classification
Patrick Foster, Georgios Papandroulidakis, Alex Serb +1
Recent advances in machine learning and neuro-inspired systems enabled the increased interest in efficient pattern recognition at the edge. A wide variety of applications, such as…
Text Classification in Memristor-based Spiking Neural Networks
Jinqi Huang, Alex Serb, Spyros Stathopoulos +1
Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementatio…