113 citations · 398 across the 22 of their papers we have counts for
22 papers
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation
Chih-Chyau Yang, Tian-Sheuan Chang
Low power deep learning accelerators on the speech processing enable real-time applications on edge devices. However, most of the existing accelerators suffer from high power consu…
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator with Decoupled Asymmetric Convolution
Tun-Hao Yang, Tian-Sheuan Chang
Deep learning-driven superresolution (SR) outperforms traditional techniques but also faces the challenge of high complexity and memory bandwidth. This challenge leads many acceler…
Real-Time Wearable Gait Phase Segmentation For Running And Walking
Jien-De Sui, Wei-Han Chen, Tzyy-Yuang Shiang +1
Previous gait phase detection as convolutional neural network (CNN) based classification task requires cumbersome manual setting of time delay or heavy overlapped sliding windows t…
Deep Gait Tracking With Inertial Measurement Unit
Jien De Sui, Tian Sheuan Chang
This paper presents a convolutional neural network based foot motion tracking with only six-axis Inertial-Measurement-Unit (IMU) sensor data. The presented approach can adapt to va…
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization
Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh Jye Jou
Keyword spotting has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always-on nature and the variety of speech, it ne…
Row-wise Accelerator for Vision Transformer
Hong-Yi Wang, Tian-Sheuan Chang
Following the success of the natural language processing, the transformer for vision applications has attracted significant attention in recent years due to its excellent performan…
A Real Time Super Resolution Accelerator with Tilted Layer Fusion
An-Jung Huang, Kai-Chieh Hsu, Tian-Sheuan Chang
Deep learning based superresolution achieves high-quality results, but its heavy computational workload, large buffer, and high external memory bandwidth inhibit its usage in mobil…
Hardware-Robust In-RRAM-Computing for Object Detection
Yu-Hsiang Chiang, Cheng En Ni, Yun Sung +3
In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However,…
IMU Based Deep Stride Length Estimation With Self-Supervised Learning
Jien-De Sui, Tian-Sheuan Chang
Stride length estimation using inertial measurement unit (IMU) sensors is getting popular recently as one representative gait parameter for health care and sports training. The tra…
Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model
Yi-An Chen, Jien-De Sui, Tian-Sheuan Chang
Gait phase detection with convolution neural network provides accurate classification but demands high computational cost, which inhibits real time low power on-sensor processing.…
VSCNN: Convolution Neural Network Accelerator With Vector Sparsity
Kuo-Wei Chang, Tian-Sheuan Chang
Hardware accelerator for convolution neural network (CNNs) enables real time applications of artificial intelligence technology. However, most of the accelerators only support dens…
VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network
Kuo-Wei Chang, Tian-Sheuan Chang
Hardware accelerators for convolution neural networks (CNNs) enable real-time applications of artificial intelligence technology. However, most of the existing designs suffer from…
Efficient Accelerator for Dilated and Transposed Convolution with Decomposition
Kuo-Wei Chang, Tian-Sheuan Chang
Hardware acceleration for dilated and transposed convolution enables real time execution of related tasks like segmentation, but current designs are specific for these convolutiona…
Pre-RTL DNN Hardware Evaluator With Fused Layer Support
Chih-Chyau Yang, Tian-Sheuan Chang
With the popularity of the deep neural network (DNN), hardware accelerators are demanded for real time execution. However, lengthy design process and fast evolving DNN models make…
A Secure File Sharing System Based on IPFS and Blockchain
Hsiao-Shan Huang, Tian-Sheuan Chang, Jhih-Yi Wu
There is a great interest in many approaches towards blockchain in providing a solution to record transactions in a decentralized way. However, there are some limitations when stor…
A Real Time 1280x720 Object Detection Chip With 585MB/s Memory Traffic
Kuo-Wei Chang, Hsu-Tung Shih, Tian-Sheuan Chang +4
Memory bandwidth has become the real-time bottleneck of current deep learning accelerators (DLA), particularly for high definition (HD) object detection. Under resource constraints…
PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting
Shu-Hung Kuo, Tian-Sheuan Chang
Computing-in-memory (CIM) has attracted significant attentions in recent years due to its massive parallelism and low power consumption. However, current CIM designs suffer from la…
VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator
Hong-Han Lien, Chung-Wei Hsu, Tian-Sheuan Chang
Spiking neural networks (SNNs) that enable low-power design on edge devices have recently attracted significant research. However, the temporal characteristic of SNNs causes high l…
Zebra: Memory Bandwidth Reduction for CNN Accelerators With Zero Block Regularization of Activation Maps
Hsu-Tung Shih, Tian-Sheuan Chang
The large amount of memory bandwidth between local buffer and external DRAM has become the speedup bottleneck of CNN hardware accelerators, especially for activation maps. To reduc…
Sparse Compressed Spiking Neural Network Accelerator for Object Detection
Hong-Han Lien, Tian-Sheuan Chang
Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary…
BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention
Dun-Hao Yang, Tian-Sheuan Chang
Increasingly, convolution neural network (CNN) based super resolution models have been proposed for better reconstruction results, but their large model size and complicated struct…
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou +6
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses because it significantly co…