VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator

Abstract

Spiking neural networks (SNNs) that enable low-power design on edge devices have recently attracted significant research. However, the temporal characteristic of SNNs causes high latency, high bandwidth and high energy consumption for the hardware. In this work, we propose a binary weight spiking model with IF-based Batch Normalization for small time steps and low hardware cost when direct training with input encoding layer and spatio-temporal back propagation (STBP). In addition, we propose a vectorwise hardware accelerator that is reconfigurable for different models, inference time steps and even supports the encoding layer to receive multi-bit input. The required memory bandwidth is further reduced by two-layer fusion mechanism. The implementation result shows competitive accuracy on the MNIST and CIFAR-10 datasets with only 8 time steps, and achieves power efficiency of 25.9 TOPS/W.

arXiv comment5 pages, 8 figures, published in IEEE ISCAS 2021

References in corpus (5)

• Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift
• Spatio-Temporal Backpropagation for Training High-performance Spiking Neural Networks
• Binarized Neural Networks
• MorphIC: A 65-nm 738k-Synapse/mm${}^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning
• Direct Training for Spiking Neural Networks: Faster, Larger, Better

Cited by in corpus (1)

• Sparse Compressed Spiking Neural Network Accelerator for Object Detection