20 citations · 82 across the 14 of their papers we have counts for
17 papers
Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference
Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat +4
Convolutional Neural Networks (CNNs) are used in a wide range of applications, with full-precision CNNs achieving high accuracy at the expense of portability. Recent progress in qu…
Statistical Hardware Design With Multi-model Active Learning
Alireza Ghaffari, Masoud Asgharian, Yvon Savaria
With the rising complexity of numerous novel applications that serve our modern society comes the strong need to design efficient computing platforms. Designing efficient hardware…
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference
MohammadHossein AskariHemmat, Theo Dupuis, Yoan Fournier +8
In this paper, we present Quark, an integer RISC-V vector processor specifically tailored for sub-byte DNN inference. Quark is implemented in GlobalFoundries' 22FDX FD-SOI technolo…
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU
Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk +3
We present a DNN accelerator that allows inference at arbitrary precision with dedicated processing elements that are configurable at the bit level. Our DNN accelerator has 8 Proce…
QReg: On Regularization Effects of Quantization
MohammadHossein AskariHemmat, Reyhane Askari Hemmat, Alex Hoffman +6
In this paper we study the effects of quantization in DNN training. We hypothesize that weight quantization is a form of regularization and the amount of regularization is correlat…
Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation
Julien Posso, Guy Bois, Yvon Savaria
Spacecraft pose estimation is an essential computer vision application that can improve the autonomy of in-orbit operations. An ESA/Stanford competition brought out solutions that…
MemSE: Fast MSE Prediction for Noisy Memristor-Based DNN Accelerators
Jonathan Kern, Sébastien Henwood, Gonçalo Mordido +4
Memristors enable the computation of matrix-vector multiplications (MVM) in memory and, therefore, show great potential in highly increasing the energy efficiency of deep neural ne…
Rethinking Pareto Frontier for Performance Evaluation of Deep Neural Networks
Vahid Partovi Nia, Alireza Ghaffari, Mahdi Zolnouri +1
Performance optimization of deep learning models is conducted either manually or through automatic architecture search, or a combination of both. On the other hand, their performan…
Bridging the Gap: FPGAs as Programmable Switches
Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva +2
The emergence of P4, a domain specific language, coupled to PISA, a domain specific architecture, is revolutionizing the networking field. P4 allows to describe how packets are pro…
CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA
Alireza Ghaffari, Yvon Savaria
Convolutional Neural Networks (CNNs) have a major impact on our society because of the numerous services they provide. On the other hand, they require considerable computing power.…
Layerwise Noise Maximisation to Train Low-Energy Deep Neural Networks
Sébastien Henwood, François Leduc-Primeau, Yvon Savaria
Deep neural networks (DNNs) depend on the storage of a large number of parameters, which consumes an important portion of the energy used during inference. This paper considers the…
U-Net Fixed-Point Quantization for Medical Image Segmentation
MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier +4
Model quantization is leveraged to reduce the memory consumption and the computation time of deep neural networks. This is achieved by representing weights and activations with a l…
Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs
Khaza Anuarul Hoque, Otmane Ait Mohamed, Yvon Savaria
SRAM-based FPGAs are popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiation-induced Single Event Upsets (SEUs).…
SHIP: A Scalable High-performance IPv6 Lookup Algorithm that Exploits Prefix Characteristics
Thibaut Stimpfling, Normand Bélanger, J. M. Pierre Langlois +1
Due to the emergence of new network applications, current IP lookup engines must support high-bandwidth, low lookup latency and the ongoing growth of IPv6 networks. However, existi…
Fast and Flexible Software Polar List Decoders
Mathieu Léonardon, Adrien Cassagne, Camille Leroux +3
Flexibility is one mandatory aspect of channel coding in modern wireless communication systems. Among other things, the channel decoder has to support several code lengths and code…
Formal Analysis of SEU Mitigation for Early Dependability and Performability Analysis of FPGA-based Space Applications
Khaza Anuarul Hoque, Otmane Ait Mohamed, Yvon Savaria
SRAM-based FPGAs are increasingly popular in the aerospace industry due to their field programmability and low cost. However, they suffer from cosmic radiation induced Single Event…
On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations
Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria +2
Experimental means to characterize delay faults induced by bit flips and SEUs in I/O blocks of SRAM-based FPGAs are proposed. A delay fault up to 6.2ns sensitized by an events chai…