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20162023
most citedLogic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism

37 citations · 133 across the 25 of their papers we have counts for

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16 papers · 1 filter

cs.LG20231 cited

INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search

Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan +2

Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optim…

cs.LG2023

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

Jason Blocklove, Siddharth Garg, Ramesh Karri +1

Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDL…

cs.LG2023

Hyper-parameter Tuning for Fair Classification without Sensitive Attribute Access

Akshaj Kumar Veldanda, Ivan Brugere, Sanghamitra Dutta +2

Fair machine learning methods seek to train models that balance model performance across demographic subgroups defined over sensitive attributes like race and gender. Although sens…

cs.LG2022

Privacy-Preserving Collaborative Learning through Feature Extraction

Alireza Sarmadi, Hao Fu, Prashanth Krishnamurthy +2

We propose a framework in which multiple entities collaborate to build a machine learning model while preserving privacy of their data. The approach utilizes feature embeddings fro…

cs.LG2022

An Upper Bound for the Distribution Overlap Index and Its Applications

Hao Fu, Prashanth Krishnamurthy, Siddharth Garg +1

This paper proposes an easy-to-compute upper bound for the overlap index between two probability distributions without requiring any knowledge of the distribution models. The compu…

cs.LG20221 cited

Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis

Animesh Basak Chowdhury, Benjamin Tan, Ryan Carey +3

Generating sub-optimal synthesis transformation sequences ("synthesis recipe") is an important problem in logic synthesis. Manually crafted synthesis recipes have poor quality. Sta…