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20152023
most citedPipeDream: Fast and Efficient Pipeline Parallel DNN Training

95 citations · 359 across the 21 of their papers we have counts for

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Showing 2018Show all

7 papers · 1 filter

cs.DC2018★ 95 cited

PipeDream: Fast and Efficient Pipeline Parallel DNN Training

Aaron Harlap, Deepak Narayanan, Amar Phanishayee +4

PipeDream is a Deep Neural Network(DNN) training system for GPUs that parallelizes computation by pipelining execution across multiple machines. Its pipeline parallel computing mod…

cs.AR2018★ 3 cited

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems

Lavanya Subramanian, Vivek Seshadri, Yoongu Kim +2

This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significa…

cs.AR2018★ 2 cited

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency

Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar +4

This paper summarizes the idea of ChargeCache, which was published in HPCA 2016 [51], and examines the work's significance and future potential. DRAM latency continues to be a crit…

cs.AR2018★ 12 cited

RowClone: Accelerating Data Movement and Initialization Using DRAM

Vivek Seshadri, Yoongu Kim, Chris Fallin +8

In existing systems, to perform any bulk data movement operation (copy or initialization), the data has to first be read into the on-chip processor, all the way into the L1 cache,…

cs.AR2018

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost

Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3

This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…

cs.AR2018★ 1 cited

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins

Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4

This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechani…

cs.AR2018★ 3 cited

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism

Yoongu Kim, Vivek Seshadri, Donghyuk Lee +2

This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was published in ISCA 2012, and examines the work's significance and future potential. Modern DRA…