95 citations · 359 across the 21 of their papers we have counts for
22 papers
X-RiSAWOZ: High-Quality End-to-End Multilingual Dialogue Datasets and Few-shot Agents
Mehrad Moradshahi, Tianhao Shen, Kalika Bali +16
Task-oriented dialogue research has mainly focused on a few popular languages like English and Chinese, due to the high dataset creation cost for a new language. To reduce the cost…
MinUn: Accurate ML Inference on Microcontrollers
Shikhar Jaiswal, Rahul Kiran Kranti Goli, Aayan Kumar +2
Running machine learning inference on tiny devices, known as TinyML, is an emerging research area. This task requires generating inference code that uses memory frugally, a task th…
Annotated Speech Corpus for Low Resource Indian Languages: Awadhi, Bhojpuri, Braj and Magahi
Ritesh Kumar, Siddharth Singh, Shyam Ratan +6
In this paper we discuss an in-progress work on the development of a speech corpus for four low-resource Indo-Aryan languages -- Awadhi, Bhojpuri, Braj and Magahi using the field m…
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Nikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma +2
Recent breakthroughs in ML have produced new classes of models that allow ML inference to run directly on milliwatt-powered IoT devices. On one hand, existing ML-to-FPGA compilers…
Multilingual and code-switching ASR challenges for low resource Indian languages
Anuj Diwan, Rakesh Vaideeswaran, Sanket Shah +19
Recently, there is increasing interest in multilingual automatic speech recognition (ASR) where a speech recognition system caters to multiple low resource languages by taking adva…
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
Nastaran Hajinazar, Pratyush Patel, Minesh Patel +7
Computers continue to diversify with respect to system designs, emerging memory technologies, and application memory demands. Unfortunately, continually adapting the conventional v…
In-DRAM Bulk Bitwise Execution Engine
Vivek Seshadri, Onur Mutlu
Many applications heavily use bitwise operations on large bitvectors as part of their computation. In existing systems, performing such bulk bitwise operations requires the process…
Dataplant: Enhancing System Security with Low-Cost In-DRAM Value Generation Primitives
Lois Orosa, Yaohua Wang, Ivan Puddu +13
DRAM manufacturers have been prioritizing memory capacity, yield, and bandwidth for years, while trying to keep the design complexity as simple as possible. DRAM chips do not carry…
PipeDream: Fast and Efficient Pipeline Parallel DNN Training
Aaron Harlap, Deepak Narayanan, Amar Phanishayee +4
PipeDream is a Deep Neural Network(DNN) training system for GPUs that parallelizes computation by pipelining execution across multiple machines. Its pipeline parallel computing mod…
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim +2
This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significa…
Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency
Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar +4
This paper summarizes the idea of ChargeCache, which was published in HPCA 2016 [51], and examines the work's significance and future potential. DRAM latency continues to be a crit…
RowClone: Accelerating Data Movement and Initialization Using DRAM
Vivek Seshadri, Yoongu Kim, Chris Fallin +8
In existing systems, to perform any bulk data movement operation (copy or initialization), the data has to first be read into the on-chip processor, all the way into the L1 cache,…
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechani…
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
Yoongu Kim, Vivek Seshadri, Donghyuk Lee +2
This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was published in ISCA 2012, and examines the work's significance and future potential. Modern DRA…
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM
Vivek Seshadri, Donghyuk Lee, Thomas Mullins +7
Bitwise operations are an important component of modern day programming. Many widely-used data structures (e.g., bitmap indices in databases) rely on fast bitwise operations on lar…
The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
Vivek Seshadri, Onur Mutlu
In existing systems, the off-chip memory interface allows the memory controller to perform only read or write operations. Therefore, to perform any operation, the processor must fi…
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Donghyuk Lee, Samira Khan, Lavanya Subramanian +5
Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the…
Simple DRAM and Virtual Memory Abstractions to Enable Highly Efficient Memory Systems
Vivek Seshadri
In most modern systems, the memory subsystem is managed and accessed at multiple different granularities at various resources. We observe that such multi-granularity management res…
Adaptive-Latency DRAM (AL-DRAM)
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built into the D…
Tiered-Latency DRAM (TL-DRAM)
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in m…
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri +2
In a multicore system, applications running on different cores interfere at main memory. This inter-application interference degrades overall system performance and unfairly slows…