150 citations · 1.3k across the 73 of their papers we have counts for
3 papers · 1 filter
Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface
Donghyuk Lee, Gennady Pekhimenko, Samira Khan +2
Limited memory bandwidth is a critical bottleneck in modern systems. 3D-stacked DRAM enables higher bandwidth by leveraging wider Through-Silicon-Via (TSV) channels, but today's sy…
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
Hiroyuki Usui, Lavanya Subramanian, Kevin Chang +1
Modern SoCs integrate multiple CPU cores and Hardware Accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents.…
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri +2
In a multicore system, applications running on different cores interfere at main memory. This inter-application interference degrades overall system performance and unfairly slows…