6 citations · 6 across the 12 of their papers we have counts for
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cs.AR2014
Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware
Madhav Desai
In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in parti…
cs.AR2014★ 6 cited
On the likelihood of multiple bit upsets in logic circuits
Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai
Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the architectural level, soft errors are commonly modeled by a probabilistic bit-flip…