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cs.AR2026
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
Ayushi Agarwal, Anannya Mathur, Preeti Ranjan Panda
The system-level cache is a critical resource shared by processor cores and domain-specific accelerators in heterogeneous systems on chips (SoCs). The strict QoS requirements of ac…
cs.AR2021
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems
Lokesh Siddhu, Rajesh Kedia, Shailja Pandey +4
Processing cores and the accompanying main memory working in tandem enable the modern processors. Dissipating heat produced from computation, memory access remains a significant pr…