2 papers
cs.AR2026
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
Ayushi Agarwal, Anannya Mathur, Preeti Ranjan Panda
The system-level cache is a critical resource shared by processor cores and domain-specific accelerators in heterogeneous systems on chips (SoCs). The strict QoS requirements of ac…
math.CA2023
Real analytic functions and monomial curves
János Kollár
We show that a function is real analytic at the origin iff it is arc-analytic, has a subanalytic graph, and its restriction to every monomial curve is analytic. This complements re…