1 citations · 1 across the 4 of their papers we have counts for
4 papers
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators
Ayushi Agarwal, Anannya Mathur, Preeti Ranjan Panda
The system-level cache is a critical resource shared by processor cores and domain-specific accelerators in heterogeneous systems on chips (SoCs). The strict QoS requirements of ac…
Real analytic functions and monomial curves
János Kollár
We show that a function is real analytic at the origin iff it is arc-analytic, has a subanalytic graph, and its restriction to every monomial curve is analytic. This complements re…
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems
Lokesh Siddhu, Rajesh Kedia, Shailja Pandey +4
Processing cores and the accompanying main memory working in tandem enable the modern processors. Dissipating heat produced from computation, memory access remains a significant pr…
Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda +1
In this report, we report some fundamental results and bounds on the number of messages and storage required to implement barriers using futuristic on-chip optical and RF networks.…