27 papers
Hardware Design and Security in the Era of Chiplets and LLMs
Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz +1
The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic…
FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?
Weimin Fu, Hejia Zhang, Minghao Shao +6
Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines…
Security Analysis for SCONE Logic Locking
Akashdeep Saha, Mohammed Nabeel, Johann Knechtel +2
SCONE [DAC'25] expands a logic locking interface with additional encoded inputs derived from the original primary inputs, and admits two realizations: a \textit{with-ES} variant, w…
Learning Structural Manipulability in Gate-Level Netlists Using Graph Neural Networks
Rupesh Raj Karn, Ozgur Sinanoglu
Gate-level netlists exhibit intrinsic structural properties that influence signal propagation independently of functional simulation. We define a topology-driven structural manipul…
Leaking Circuit Secrets: Gradient Leakage Attacks on Graph Neural Networks
Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
As graph neural networks (GNNs) become standard tools for critical tasks in circuit design and analysis, their security and privacy risks require careful attention. Here, we presen…
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
Saideep Sreekumar, Zeng Wang, Akashdeep Saha +6
Hardware Trojans (HTs) remain a critical threat because learning-based detectors often overfit to narrow trigger/payload patterns and small, stylized benchmarks. We introduce Troja…