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20242026
most citedHarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking

1 citations · 1 across the 15 of their papers we have counts for

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cs.CR2024

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation

Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam +4

Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL…

cs.CR2024

Lightweight Countermeasures Against Static Power Side-Channel Attacks

Jitendra Bhandari, Mohammed Nabeel, Likhitha Mankali +3

This paper presents a novel defense strategy against static power side-channel attacks (PSCAs), a critical threat to cryptographic security. Our method is based on (1) carefully tu…

cs.CR2024

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search

Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel +4

Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, negl…

cs.LG2024

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust

Zeng Wang, Lilas Alrahis, Likhitha Mankali +2

Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with trem…

cs.CR2024

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans

Fangzhou Wang, Qijing Wang, Lilas Alrahis +7

Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many secu…