6 papers
Development of LGAD Sensor Technology on 12 inch Wafers for 3D Integration with advanced CMOS processes
Ron Lipton, Julie Segal, Angela Kok +10
We report on the design, simulation, and initial testing of Low Gain Avalanche Diode (LGAD) sensors fabricated in 65 nm CMOS technology on 12 inch wafers. These sensors were develo…
Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS
Adam Quinn, Troy England, Andrew Li +1
Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS m…
PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL
Ahan Datta, Andrew Arzac, Davide Braga +14
Picosecond level timing resolution is a prerequisite capability for improved coincidence matching, time-of-flight measurements, and secondary vertex reconstruction. Here, we presen…
A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference
Fabricio Alcalde Bessia, Claudio Chavez, Troy England +6
The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double…
Design of an 8-Channel 40 GS/s 20 mW/Ch Waveform Sampling ASIC in 65 nm CMOS
Jinseo Park, Evan Angelico, Andrew Arzac +14
1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5…
A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC
Fabricio Alcalde Bessia, Troy England, Hongzhi Sun +6
The \emph{MIDNA} application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperat…