7 papers · 1 filter
UniRTL: Unifying Code and Graph for Robust RTL Representation Learning
Yi Liu, Hongji Zhang, Lei Chen +2
Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rel…
Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning
Yi Liu, Hongji Zhang, Yiwen Wang +4
Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance met…
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Dimitris Tsaras, Xing Li, Lei Chen +2
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Opera…
Circuit Transformer: A Transformer That Preserves Logical Equivalence
Xihan Li, Xing Li, Lei Chen +3
Implementing Boolean functions with circuits consisting of logic gates is fundamental in digital computer design. However, the implemented circuit must be exactly equivalent, which…
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization
Faezeh Faez, Raika Karimi, Yingxue Zhang +4
Electronic Design Automation (EDA) is essential for IC design and has recently benefited from AI-based techniques to improve efficiency. Logic synthesis, a key EDA stage, transform…
SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation
Xinyi Zhou, Xing Li, Yingzhao Lian +6
We introduce SeaDAG, a semi-autoregressive diffusion model for conditional generation of Directed Acyclic Graphs (DAGs). Considering their inherent layer-wise structure, we simulat…