7 papers
UniRTL: Unifying Code and Graph for Robust RTL Representation Learning
Yi Liu, Hongji Zhang, Lei Chen +2
Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rel…
Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning
Yi Liu, Hongji Zhang, Yiwen Wang +4
Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance met…
SwiftMem: Fast Agentic Memory via Query-aware Indexing
Anxin Tian, Yiming Li, Xing Li +5
Agentic memory systems have become critical for enabling LLM agents to maintain long-term context and retrieve relevant information efficiently. However, existing memory frameworks…
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
Chengxi Li, Yang Sun, Lei Chen +3
This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and t…
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Dimitris Tsaras, Xing Li, Lei Chen +2
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Opera…
Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers
Raika Karimi, Faezeh Faez, Yingxue Zhang +4
Contemporary hardware design benefits from the abstraction provided by high-level logic gates, streamlining the implementation of logic circuits. Logic Synthesis Optimization (LSO)…