50 citations · 75 across the 6 of their papers we have counts for
3 papers · 1 filter
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona +3
As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values compr…
An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
Bartomeu Alorda, Cristian Carmona, Gabriel Torrens +1
Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimati…
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results
Gabriel Torrens, Ivan de Paul, Bartomeu Alorda +2
Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -- the word-line voltage margin (VWLVM) -…