50 citations · 75 across the 8 of their papers we have counts for
8 papers
SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram
Gabriel Torrens, Abdel Alheyasat, Bartomeu Alorda +1
This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applicatio…
Estimation during Design Phases of Suitable SRAM Cells for PUF Applications Using Separatrix and Mismatch Metrics
Abdel Alheyasat, Gabriel Torrens, Sebastia A. Bota +1
Physically unclonable functions (PUFs) are used as low-cost cryptographic primitives in device authentication and secret key creation. SRAM-PUFs are well-known as entropy sources;…
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona +3
As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values compr…
Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
Daniel Malagon, Gabriel Torrens, Jaume Segura +1
We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistors (6T) and eight-transistors (8T) bit-cells S…
An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
Bartomeu Alorda, Cristian Carmona, Gabriel Torrens +1
Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimati…
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results
Gabriel Torrens, Ivan de Paul, Bartomeu Alorda +2
Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -- the word-line voltage margin (VWLVM) -…
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
J. L. Rossello, V. Canals, S. A. Bota +2
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperatu…
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs
S. A. Bota, M. Rosales, J. L. Rossello +1
In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses…