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cs.AR2026
Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure
Chengjia Liu, Priyadarsi Mishra, David Kebo Houngninou +3
Last-mile functional coverage closure for modern chip designs remains costly because a mature UVM environment exposes many controls while direct hits on the remaining bins are spar…
cs.AR2026
EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis
Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5
Modern chip design relies on electronic design automation (EDA) tools that generate large, heterogeneous artifacts, including source files, scripts, logs, netlists, and reports. An…
cs.AR2025
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
Fenghua Wu, Evan Pan, Rahul Kande +5
SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, la…