5 papers
Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure
Chengjia Liu, Priyadarsi Mishra, David Kebo Houngninou +3
Last-mile functional coverage closure for modern chip designs remains costly because a mature UVM environment exposes many controls while direct hits on the remaining bins are spar…
EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis
Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5
Modern chip design relies on electronic design automation (EDA) tools that generate large, heterogeneous artifacts, including source files, scripts, logs, netlists, and reports. An…
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis
Surya Jasper, Minh Luu, Evan Pan +4
Hardware complexity continues to strain verification resources, motivating the adoption of machine learning (ML) methods to improve debug efficiency. However, ML-assisted debugging…
VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration
Minh Luu, Surya Jasper, Khoi Le +4
Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine lear…
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
Fenghua Wu, Evan Pan, Rahul Kande +5
SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, la…