91 citations · 154 across the 5 of their papers we have counts for
5 papers
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Zhiyao Xie, Rongjian Liang, Xiaoqing Xu +3
Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow. However, the bulk of net length information is not availab…
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Zhiyao Xie, Haoxing Ren, Brucek Khailany +4
IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques for fixing its violati…
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang +7
Design flow parameters are of utmost importance to chip design quality and require a painfully long time to evaluate their effects. In reality, flow parameter tuning is usually per…
Fast IR Drop Estimation with Machine Learning
Zhiyao Xie, Hai Li, Xiaoqing Xu +2
IR drop constraint is a fundamental requirement enforced in almost all chip designs. However, its evaluation takes a long time, and mitigation techniques for fixing violations may…
Automatic Microprocessor Performance Bug Detection
Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar +3
Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor performance rather t…