91 citations · 227 across the 8 of their papers we have counts for
8 papers
Toward Taming the Overhead Monster for Data-Flow Integrity
Lang Feng, Jiayi Huang, Jeff Huang +1
Data-Flow Integrity (DFI) is a well-known approach to effectively detecting a wide range of software attacks. However, its real-world application has been quite limited so far beca…
Automatic Routability Predictor Development Using Neural Architecture Search
Chen-Chia Chang, Jingyu Pan, Tunhou Zhang +8
The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs. Howeve…
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Zhiyao Xie, Rongjian Liang, Xiaoqing Xu +3
Net length is a key proxy metric for optimizing timing and power across various stages of a standard digital design flow. However, the bulk of net length information is not availab…
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Zhiyao Xie, Haoxing Ren, Brucek Khailany +4
IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques for fixing its violati…
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang +7
Design flow parameters are of utmost importance to chip design quality and require a painfully long time to evaluate their effects. In reality, flow parameter tuning is usually per…
Fast IR Drop Estimation with Machine Learning
Zhiyao Xie, Hai Li, Xiaoqing Xu +2
IR drop constraint is a fundamental requirement enforced in almost all chip designs. However, its evaluation takes a long time, and mitigation techniques for fixing violations may…
Automatic Microprocessor Performance Bug Detection
Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar +3
Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor performance rather t…
ALIGN: A System for Automating Analog Layout
Tonmoy Dhar, Kishor Kunal, Yaguang Li +11
ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an…