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cs.LG2025
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Shan Shen, Dingcheng Yang, Yuyang Xie +3
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulatio…
cs.LG2024
Learning-driven Physically-aware Large-scale Circuit Gate Sizing
Yuyang Ye, Peng Xu, Lizheng Ren +4
Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths…