3 papers
cs.LG2025
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Shan Shen, Dingcheng Yang, Yuyang Xie +3
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulatio…
cs.LG2024
Learning-driven Physically-aware Large-scale Circuit Gate Sizing
Yuyang Ye, Peng Xu, Lizheng Ren +4
Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths…
cs.AR2023
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design
Shixin Chen, Su Zheng, Chen Bai +4
Designing a system-on-chip (SoC) for deep neural network (DNN) acceleration requires balancing multiple metrics such as latency, power, and area. However, most existing methods ign…