6 citations · 10 across the 5 of their papers we have counts for
5 papers
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Shan Shen, Dingcheng Yang, Yuyang Xie +3
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulatio…
Learning-driven Physically-aware Large-scale Circuit Gate Sizing
Yuyang Ye, Peng Xu, Lizheng Ren +4
Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths…
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design
Shixin Chen, Su Zheng, Chen Bai +4
Designing a system-on-chip (SoC) for deep neural network (DNN) acceleration requires balancing multiple metrics such as latency, power, and area. However, most existing methods ign…
DevelSet: Deep Neural Level Set for Instant Mask Optimization
Guojin Chen, Ziyang Yu, Hongduo Liu +2
With the feature size continuously shrinking in advanced technology nodes, mask optimization is increasingly crucial in the conventional design flow, accompanied by an explosive gr…
Rethinking Graph Neural Networks for the Graph Coloring Problem
Wei Li, Ruxuan Li, Yuzhe Ma +3
Graph coloring, a classical and critical NP-hard problem, is the problem of assigning connected nodes as different colors as possible. However, we observe that state-of-the-art GNN…