3 papers
cs.AR2025
MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging
Jinwei Tang, Jiayin Qin, Nuo Xu +5
As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and…
cs.LG2025
TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
Kiran Thorat, Amit Hasan, Caiwen Ding +1
Chip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being uti…
cs.LG2024
HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
Jinwei Tang, Jiayin Qin, Kiran Thorat +5
With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL)…