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cs.AR2026
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng +1
As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Perform…
cs.LG2026
Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu +2
Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the…