1 citations · 1 across the 12 of their papers we have counts for
12 papers
HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation
Tairan Cheng, Yi Liu, Dongsheng Zuo +6
Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing an…
UniRTL: Unifying Code and Graph for Robust RTL Representation Learning
Yi Liu, Hongji Zhang, Lei Chen +2
Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rel…
From Craft to Kernel: A Governance-First Execution Architecture and Semantic ISA for Agentic Computers
Xiangyu Wen, Yuang Zhao, Xiaoyu Xu +9
The transition of agentic AI from brittle prototypes to production systems is stalled by a pervasive crisis of craft. We suggest that the prevailing orchestration paradigm-delegati…
DiffHLS: Differential Learning for High-Level Synthesis QoR Prediction with GNNs and LLM Code Embeddings
Zedong Peng, Zeju Li, Qiang Xu +1
High-Level Synthesis (HLS) compiles C/C++ into RTL, but exploring pragma-driven optimization choices remains expensive because each design point requires time-consuming synthesis.…
FormalRTL: Verified RTL Synthesis at Scale
Kezhi Li, Min Li, Xiangyu Wen +4
Large language models (LLMs) have demonstrated significant potential in automating hardware synthesis, yet substantial barriers remain for industrial-scale, datapath-centric design…
CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
Zhengyuan Shi, Jingxin Wang, Tairan Cheng +3
Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downst…
DeepRTL2: A Versatile Model for RTL-Related Tasks
Yi Liu, Hongji Zhang, Yunhao Zhou +3
The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in regi…
ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
Zhengyuan Shi, Zeju Li, Chengyu Ma +19
We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RT…
Speculative Decoding for Verilog: Speed and Quality, All in One
Changran Xu, Yi Liu, Yunhao Zhou +3
The rapid advancement of large language models (LLMs) has revolutionized code generation tasks across various programming languages. However, the unique characteristics of programm…
DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis
Zeju Li, Changran Xu, Zhengyuan Shi +11
This paper introduces DeepCircuitX, a comprehensive repository-level dataset designed to advance RTL (Register Transfer Level) code understanding, generation, and power-performance…
DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model
Yi Liu, Changran Xu, Yunhao Zhou +2
Recent advancements in large language models (LLMs) have shown significant potential for automating hardware description language (HDL) code generation from high-level natural lang…
Dyve: Thinking Fast and Slow for Dynamic Process Verification
Jianyuan Zhong, Zeju Li, Zhijian Xu +2
We present Dyve, a dynamic process verifier that enhances reasoning error detection in large language models by integrating fast and slow thinking, inspired by Kahneman's Systems T…