6 papers
DeepRTL2: A Versatile Model for RTL-Related Tasks
Yi Liu, Hongji Zhang, Yunhao Zhou +3
The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in regi…
ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
Zhengyuan Shi, Zeju Li, Chengyu Ma +19
We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RT…
Speculative Decoding for Verilog: Speed and Quality, All in One
Changran Xu, Yi Liu, Yunhao Zhou +3
The rapid advancement of large language models (LLMs) has revolutionized code generation tasks across various programming languages. However, the unique characteristics of programm…
DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis
Zeju Li, Changran Xu, Zhengyuan Shi +11
This paper introduces DeepCircuitX, a comprehensive repository-level dataset designed to advance RTL (Register Transfer Level) code understanding, generation, and power-performance…
DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model
Yi Liu, Changran Xu, Yunhao Zhou +2
Recent advancements in large language models (LLMs) have shown significant potential for automating hardware description language (HDL) code generation from high-level natural lang…
Dyve: Thinking Fast and Slow for Dynamic Process Verification
Jianyuan Zhong, Zeju Li, Zhijian Xu +2
We present Dyve, a dynamic process verifier that enhances reasoning error detection in large language models by integrating fast and slow thinking, inspired by Kahneman's Systems T…