25 citations · 34 across the 17 of their papers we have counts for
5 papers · 1 filter
A Progressive Approach to Synthesizable RTL Design Generation Using LLMs
Xiangfei Kong, Tasnim Tabassum, Marwan Abdelwahab +1
Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rat…
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
Sazzadul Islam, Tasnim Tabassum, Hao Zheng
Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structur…
AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
Bardia Nadimi, Hao Zheng
Understanding communication behavior in modern system-on-chip (SoC) designs is critical for functional verification, performance analysis, and post-silicon debugging. Communication…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…