25 citations · 34 across the 17 of their papers we have counts for
18 papers
The Window Is in the Reasoning: When LLM Agents Decide to Follow Prompt Injections
Haoxuan Jia, Yang Liu, Bin Chong +13
LLM agents that read untrusted content can be hijacked by prompt injections. Runtime monitors that try to catch a hijack before the agent acts, and benchmarks that score each task…
Harness-agnostic detection and immunization of reward hacking in self-evolving language models
Rongxin Yang, Yang Liu, Shang Luo +10
Self-evolving language models improve by proposing candidate updates and keeping whatever raises a visible score. When that score is an imperfect proxy for the capability one actua…
Safety Does Not Compose: Non-Decaying Loop State for Autonomous LLM Agents
Chenhao Wu, Haoxuan Jia, Yang Liu +11
Large language model agents are increasingly deployed as autonomous loops. Starting from one human goal, such a system repeatedly discovers work, plans, executes tool calls, verifi…
Hindsight Memory-PRM: Supervising Memory Management with Auditable Hindsight Credit
Haoxuan Jia, Yang Liu, Yingguang Yang +14
Memory operations of long-horizon LLM agents are hard to supervise: an operation's value is unobservable when it is taken. But they are special -- they leave machine-readable evide…
LLM-Assisted Detection and Repair of Hardware Security Vulnerabilities in Verilog Designs
Ethen Santana, Gabriel Gyaase, Hao Zheng
Hardware designs, like software, are susceptible to bugs that can introduce security vulnerabilities and create opportunities for malicious exploitation. Unlike software vulnerabil…
A Progressive Approach to Synthesizable RTL Design Generation Using LLMs
Xiangfei Kong, Tasnim Tabassum, Marwan Abdelwahab +1
Large language models can generate register-transfer-level (RTL) designs directly from natural language specifications. Their failures, however, arise mostly from understanding rat…
FinHarness: An Inline Lifecycle Safety Harness for Finance LLM Agents
Haoxuan Jia, Yang Liu, Bin Chong +10
Finance LLM agents must simultaneously block prompt-induced unauthorized actions and approve legitimate multi-step business workflows. However, boundary filters often miss irrevers…
SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation
Jaime Rafael Imperial, Hao Zheng
Existing Large Language Model (LLM) approaches to SystemVerilog Assertion (SVA) generation primarily focus on syntactic validity and formal verification outcomes, while semantic al…
Hallucination as Exploit: Evidence-Carrying Multimodal Agents
Guijia Zhang, Hao Zheng, Harry Yang
Multimodal agents increasingly choose tool calls from screenshots, documents, and webpages, where a false perceptual claim can turn hallucination from an answer-quality error into…
MAIGO: Mitigating Lost-in-Conversation with History-Cleaned On-Policy Self-Distillation
Haoyu Zheng, Yun Zhu, Shu Yuan +5
Large language models often solve tasks from a fully specified prompt but degrade when the same requirements unfold over multiple turns, known as the lost-in-conversation (LiC) gap…
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
Sazzadul Islam, Tasnim Tabassum, Hao Zheng
Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structur…
Calibrated Speculative Decoding: Frequency-Guided Candidate Selection for Efficient Inference
Xuwen Zhou, Fangxin Liu, Chao Wang +5
Speculative decoding accelerates autoregressive generation by letting draft tokens bypass full verification, but conventional frameworks suffer from frequent false rejections, part…
AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
Bardia Nadimi, Hao Zheng
Understanding communication behavior in modern system-on-chip (SoC) designs is critical for functional verification, performance analysis, and post-silicon debugging. Communication…
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
Bardia Nadimi, Khashayar Filom, Deming Chen +1
With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…
Inferring Message Flows From System Communication Traces
Bardia Nadimi, Hao Zheng
This paper proposes a novel method for automatically inferring message flow specifications from the communication traces of a system-on-chip (SoC) design that captures messages exc…
A Multi-Expert Large Language Model Architecture for Verilog Code Generation
Bardia Nadimi, Hao Zheng
Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation. However, the existing approaches are limited in terms of the quality…