2 citations · 2 across the 5 of their papers we have counts for
6 papers
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
Sazzadul Islam, Tasnim Tabassum, Hao Zheng
Generating synthesizable Verilog for large, hierarchical hardware designs remains a significant challenge for large language models (LLMs), which struggle to replicate the structur…
Calibrated Speculative Decoding: Frequency-Guided Candidate Selection for Efficient Inference
Xuwen Zhou, Fangxin Liu, Chao Wang +5
Speculative decoding accelerates autoregressive generation by letting draft tokens bypass full verification, but conventional frameworks suffer from frequent false rejections, part…
AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
Bardia Nadimi, Hao Zheng
Understanding communication behavior in modern system-on-chip (SoC) designs is critical for functional verification, performance analysis, and post-silicon debugging. Communication…
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
Bardia Nadimi, Khashayar Filom, Deming Chen +1
With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…