5 citations · 5 across the 10 of their papers we have counts for
11 papers
Bounded Dynamic Level Maintenance for Efficient Logic Optimization
Junfeng Liu, Qinghua Zhao, Liwei Ni +5
Logic optimization constitutes a critical phase within the Electronic Design Automation (EDA) flow, essential for achieving desired circuit power, performance, and area (PPA) targe…
BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction
Liwei Ni, Jiaxi Zhang, Shenggen Zheng +5
Boolean equivalence allows Boolean networks with identical functionality to exhibit diverse graph structures. This gives more room for exploration in logic optimization, while also…
OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis
Liwei Ni, Rui Wang, Miao Liu +10
This paper introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine learning~(ML) applications within the logic synthesis process. Previo…
Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network
Liwei Ni, Xinquan Li, Biwei Xie +1
Boolean circuit is a computational graph that consists of the dynamic directed graph structure and static functionality. The commonly used logic optimization and Boolean matching-b…
Parallel AIG Refactoring via Conflict Breaking
Ye Cai, Zonglin Yang, Liwei Ni +3
Algorithm parallelization to leverage multi-core platforms for improving the efficiency of Electronic Design Automation~(EDA) tools plays a significant role in enhancing the scalab…
Enhancing ASIC Technology Mapping via Parallel Supergate Computing
Ye Cai, Zonglin Yang, Liwei Ni +2
With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend…
MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA
Liwei Ni, Zonglin Yang, Jiaxi Zhang +6
Technology mapping is an essential step in EDA flow. However, the function of the circuit may be changed after technology mapping, and equivalence checking (EC) based verification…
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning
Liwei Ni, Zonglin Yang, Jiaxi Zhang +4
Rewriting is a common procedure in logic synthesis aimed at improving the performance, power, and area (PPA) of circuits. The traditional reconvergence-driven And-Inverter Graph (A…
Fast Exact NPN Classification with Influence-aided Canonical Form
Yonghe Zhang, Liwei Ni, Jiaxi Zhang +3
NPN classification has many applications in the synthesis and verification of digital circuits. The canonical-form-based method is the most common approach, designing a canonical f…
iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library
Xingquan Li, Simin Tao, Zengrong Huang +53
Open-source EDA shows promising potential in unleashing EDA innovation and lowering the cost of chip design. This paper presents an open-source EDA project, iEDA, aiming for buildi…
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions
Jiaxi Zhang, Shenggen Zheng, Liwei Ni +2
NPN classification is an essential problem in the design and verification of digital circuits. Most existing works explored variable symmetries and cofactor signatures to develop t…