activity
20232026
most citedRTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

95 citations · 113 across the 16 of their papers we have counts for

collaborators
Showing 2025Show all

9 papers · 1 filter

cs.AR2025

ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework

Qijun Zhang, Shang Liu, Yao Lu +2

Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power o…

cs.AR2025

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design

Qijun Zhang, Yao Lu, Mengming Li +2

Power is the primary design objective of large-scale integrated circuits (ICs), especially for complex modern processors (i.e., CPUs). Accurate CPU power evaluation requires design…

cs.AR2025

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

Wenkai Li, Yao Lu, Wenji Fang +3

Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, tradi…

cs.AR2025

AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling

Qijun Zhang, Yao Lu, Mengming Li +1

Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform early-stage power esti…

cs.SE2025

HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions

Jing Wang, Shang Liu, Yao Lu +1

High-level synthesis (HLS) accelerates hardware design by enabling the automatic translation of high-level descriptions into efficient hardware implementations. However, debugging…

cs.AR2025

Profile-Guided Temporal Prefetching

Mengming Li, Qijun Zhang, Yichuan Gao +4

Temporal prefetching shows promise for handling irregular memory access patterns, which are common in data-dependent and pointer-based data structures. Recent studies introduced on…

cs.AR2025

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph

Wenji Fang, Wenkai Li, Shang Liu +3

Circuit representation learning has shown promise in advancing Electronic Design Automation (EDA) by capturing structural and functional circuit properties for various tasks. Exist…

cs.LG2025

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

Wenji Fang, Jing Wang, Yao Lu +2

The success of foundation AI has motivated the research of circuit foundation models, which are customized to assist the integrated circuit (IC) design process. However, existing p…

cs.AR2025

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Wenji Fang, Jing Wang, Yao Lu +4

Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…