95 citations · 113 across the 16 of their papers we have counts for
18 papers
FABO: Agent-Guided Discovery of Joint Breakpoint Optimization for Timing-Driven Routing Trees
Shang Liu, Wenji Fang, Jing Wang +3
The topology of a routing tree determines how a multi-pin net branches and shares physical wire, directly affecting wirelength, congestion, capacitance, and delay. We study a centr…
COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
Yao Lu, Zhicheng Guo, Qijun Zhang +4
Advanced 3D and 3.5D IC packaging significantly improves integration density but elevates thermal management challenges due to cross-layer heat coupling and complex cooling structu…
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
Qijun Zhang, Yao Lu, Shang Liu +4
Graphics Processing Units (GPUs) have been serving as critical computation resources for large-scale parallel computations. With increasing chip complexity, power efficiency has be…
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
Wenkai Li, Yuchao Wu, Ziyan Guo +4
Accurate power analysis is critical in VLSI design, as it directly impacts power optimization strategies. However, traditional approaches are often hindered by the substantial runt…
A New Benchmark for the Appropriate Evaluation of RTL Code Optimization
Yao Lu, Shang Liu, Hangan Zhou +3
The rapid progress of artificial intelligence increasingly relies on efficient integrated circuit (IC) design. Recent studies have explored the use of large language models (LLMs)…
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
Qijun Zhang, Shang Liu, Yao Lu +2
Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power o…
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
Qijun Zhang, Yao Lu, Mengming Li +2
Power is the primary design objective of large-scale integrated circuits (ICs), especially for complex modern processors (i.e., CPUs). Accurate CPU power evaluation requires design…
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Wenkai Li, Yao Lu, Wenji Fang +3
Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, tradi…
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
Qijun Zhang, Yao Lu, Mengming Li +1
Power efficiency is a critical design objective in modern CPU design. Architects need a fast yet accurate architecture-level power evaluation tool to perform early-stage power esti…
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
Jing Wang, Shang Liu, Yao Lu +1
High-level synthesis (HLS) accelerates hardware design by enabling the automatic translation of high-level descriptions into efficient hardware implementations. However, debugging…
Profile-Guided Temporal Prefetching
Mengming Li, Qijun Zhang, Yichuan Gao +4
Temporal prefetching shows promise for handling irregular memory access patterns, which are common in data-dependent and pointer-based data structures. Recent studies introduced on…
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Wenji Fang, Wenkai Li, Shang Liu +3
Circuit representation learning has shown promise in advancing Electronic Design Automation (EDA) by capturing structural and functional circuit properties for various tasks. Exist…
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
Wenji Fang, Jing Wang, Yao Lu +2
The success of foundation AI has motivated the research of circuit foundation models, which are customized to assist the integrated circuit (IC) design process. However, existing p…
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
Wenji Fang, Jing Wang, Yao Lu +4
Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
Qijun Zhang, Mengming Li, Yao lu +1
Power efficiency is a critical design objective in modern processor design. A high-fidelity architecture-level power modeling method is greatly needed by CPU architects for guiding…
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
Shang Liu, Wenji Fang, Yao Lu +3
The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. Howe…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Wenji Fang, Yao Lu, Shang Liu +5
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) l…
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Yao Lu, Shang Liu, Qijun Zhang +1
Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design…