4 papers · 1 filter
In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs
Mostafa Darvishi
Timing degradation in SRAM-based FPGAs arises from multiple physical mechanisms that manifest differently in the routing fabric, most notably power-distribution-network (PDN) margi…
Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
Mostafa Darvishi
Selective hardening is widely employed to improve the reliability of FPGA based soft processors while limiting the overhead of full redundancy. However, existing approaches primari…
Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
Mostafa Darvishi
This paper presents a pipeline stage resolved timing characterization of a 32-bit RISC V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC platform. A unified analysis f…
A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs
Mostafa Darvishi
Floating point arithmetic remains expensive on FPGA platforms due to wide datapaths and normalization logic, motivating alternative representations that preserve dynamic range at l…