10 papers
Vulnerability-Weighted Routing of Timing-Critical Nets for Configuration-Upset-Resilient SRAM-Based FPGAs
Mostafa Darvishi
Conventional FPGA routing optimizes timing, congestion, and routability but does not distinguish routes with similar nominal performance and substantially different susceptibility…
From Routing Delay Shifts to Silent Data Corruption: Neutron-Induced SEU Effects in AXI-Based Zynq UltraScale+ MPSoCs
Mostafa Darvishi
SRAM-based FPGA system-on-chip devices are vulnerable to single-event upsets (SEUs) in configuration memory, which may perturb programmable routing resources and degrade communicat…
GRACIDIT: Graph-Circuit Digital Twin for Configuration-Induced Routing Delay Prediction in Zynq UltraScale+ FPGAs
Mostafa Darvishi
Configuration-induced perturbations in SRAM-based FPGAs may activate dormant programmable routing branches and increase path delay without immediately producing a functional error.…
Embedded Machine Learning for Microcontroller-Class Edge Devices: Data, Feature, Evaluation, and Deployment Pipelines
Mostafa Darvishi
Embedded machine learning moves inference from cloud services to resource-constrained devices that must acquire data, preprocess signals, run a model, and act within tight limits o…
In-Situ Timing Diagnosis of PDN and Configuration-Upset-Induced Routing Delay Degradation in SRAM-based FPGAs
Mostafa Darvishi
Timing degradation in SRAM-based FPGAs arises from multiple physical mechanisms that manifest differently in the routing fabric, most notably power-distribution-network (PDN) margi…
A Hybrid Residue Floating Numerical Architecture with Formal Error Bounds for High Throughput FPGA Computation
Mostafa Darvishi
Floating point arithmetic is costly on FPGA platforms due to wide datapaths, normalization, and carry propagation, motivating alternative numerical representations that improve thr…
Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
Mostafa Darvishi
Selective hardening is widely employed to improve the reliability of FPGA based soft processors while limiting the overhead of full redundancy. However, existing approaches primari…
Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
Mostafa Darvishi
This paper presents a pipeline stage resolved timing characterization of a 32-bit RISC V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC platform. A unified analysis f…
A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs
Mostafa Darvishi
Floating point arithmetic remains expensive on FPGA platforms due to wide datapaths and normalization logic, motivating alternative representations that preserve dynamic range at l…
Practical Timing Closure in FPGA and ASIC Designs: Methods, Challenges, and Case Studies
Mostafa Darvishi
This paper presents an in-depth analysis of timing closure challenges and constraints in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs)…