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cs.AR2026
A Hybrid Residue Floating Numerical Architecture with Formal Error Bounds for High Throughput FPGA Computation
Mostafa Darvishi
Floating point arithmetic is costly on FPGA platforms due to wide datapaths, normalization, and carry propagation, motivating alternative numerical representations that improve thr…
cs.AR2025
Practical Timing Closure in FPGA and ASIC Designs: Methods, Challenges, and Case Studies
Mostafa Darvishi
This paper presents an in-depth analysis of timing closure challenges and constraints in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs)…