260 citations · 468 across the 20 of their papers we have counts for
8 papers · 1 filter
Differential Stochastic Simulated Annealing Processor for Fully Connected 2048-Spin Optimization
Naoya Onizawa, Md Mohaimenul Alam, Sean Smithson +2
A 2,048-spin fully connected annealing processor based on differential stochastic simulated annealing (DSSA) is presented as an architectural design in TSMC 28 nm CMOS with a 3 mm…
Efficient CMOS Invertible Logic Using Stochastic Computing
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer +2
Invertible logic can operate in one of two modes: 1) a forward mode, in which inputs are presented and a single, correct output is produced, and 2) a reverse mode, in which the out…
Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture
Naoya Onizawa, Taiga Kubuta, Duckgyu Shin +1
Probabilistic bits (p-bits) offer an energy-efficient hardware abstraction for stochastic optimization; however, existing p-bit-based simulated annealing accelerators suffer from p…
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
R. Kanda, H. L. Blevec, N. Onizawa +3
In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-bas…
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
R. Kanda, N. Onizawa, M. Leonardon +2
This study aims to ensure consistency in accuracy throughout the entire design flow in the implementation of edge AI hardware for few-shot learning, by implementing fixed-point dat…
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing
Duckgyu Shin, Naoya Onizawa, Warren J. Gross +1
Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the proble…
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks
Hooman Jarollahi, Naoya Onizawa, Warren J. Gross
Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardw…
A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa +1
A low-power Content-Addressable-Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The…