260 citations · 468 across the 20 of their papers we have counts for
21 papers
Error-Rate Reduction in LDPC Decoding via Bit-Aligned Temporal Reinforcement in Parallel Probabilistic-Bit Dynamics
Naoya Onizawa, Takahiro Hanyu
Probabilistic bits (p-bits) provide a physical and algorithmic primitive for stochastic inference, but highly parallel updates can alter their collective dynamics. We study the dec…
Differential Stochastic Simulated Annealing Processor for Fully Connected 2048-Spin Optimization
Naoya Onizawa, Md Mohaimenul Alam, Sean Smithson +2
A 2,048-spin fully connected annealing processor based on differential stochastic simulated annealing (DSSA) is presented as an architectural design in TSMC 28 nm CMOS with a 3 mm…
A Unified Performance-Cost Landscape of Parallel p-bit Ising Machines Based on Update Dynamics
Naoya Onizawa, Takahiro Hanyu
Parallel p-bit Ising machines are a promising platform for fast and energy-efficient combinatorial optimization, but their scalability depends on update synchronization, hardware d…
Efficient CMOS Invertible Logic Using Stochastic Computing
Sean C. Smithson, Naoya Onizawa, Brett H. Meyer +2
Invertible logic can operate in one of two modes: 1) a forward mode, in which inputs are presented and a single, correct output is produced, and 2) a reverse mode, in which the out…
Efficient Few-Shot Learning for Edge AI via Knowledge Distillation on MobileViT
Shuhei Tsuyuki, Reda Bensaid, Jérémy Morlier +4
Efficient and adaptable deep learning models are an important area of deep learning research, driven by the need for highly efficient models on edge devices. Few-shot learning enab…
Scylla at APOGEE: The Impact of Starbursts on the Chemical Evolution of the Magellanic Clouds
Ivanna Escala, Kristen B. W. McQuinn, Sten Hasselquist +11
Owing to their proximity to the Milky Way, the Large and Small Magellanic Clouds (L/SMC) uniquely probe the evolution of low-mass galaxies undergoing mutual interactions. In this w…
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing
Kota Katsuki, Duckgyu Shin, Naoya Onizawa +1
In this paper, we evaluate stochastic-computing simulated annealing (SC-SA) for solving large-scale combinatorial optimization problems. SC-SA is designed using stochastic computin…
Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture
Naoya Onizawa, Taiga Kubuta, Duckgyu Shin +1
Probabilistic bits (p-bits) offer an energy-efficient hardware abstraction for stochastic optimization; however, existing p-bit-based simulated annealing accelerators suffer from p…
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
R. Kanda, H. L. Blevec, N. Onizawa +3
In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-bas…
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
R. Kanda, N. Onizawa, M. Leonardon +2
This study aims to ensure consistency in accuracy throughout the entire design flow in the implementation of edge AI hardware for few-shot learning, by implementing fixed-point dat…
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing
Duckgyu Shin, Naoya Onizawa, Warren J. Gross +1
Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the proble…
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians
Naoya Onizawa, Takahiro Hanyu
This paper introduces CMOS invertible-logic (CIL) circuits based on many-body Hamiltonians. CIL can realize probabilistic forward and backward operations of a function by annealing…
Enhanced Convergence in p-bit Based Simulated Annealing with Partial Deactivation for Large-Scale Combinatorial Optimization Problems
Naoya Onizawa, Takahiro Hanyu
This article critically investigates the limitations of the simulated annealing algorithm using probabilistic bits (pSA) in solving large-scale combinatorial optimization problems.…
Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips
Naoya Onizawa, Daisaku Katagiri, Warren J. Gross +1
This paper introduces an analog-to-stochastic converter using a magnetic tunnel junction (MTJ) device for vision chips based on stochastic computation. Stochastic computation has b…
GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling
Naoya Onizawa, Takahiro Hanyu
Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and…
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing
Naoya Onizawa, Kyo Kuroki, Duckgyu Shin +1
This paper presents a local energy distribution based hyperparameter determination for stochastic simulated annealing (SSA). SSA is capable of solving combinatorial optimization pr…
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems
Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin +2
In this paper, we introduce stochastic simulated quantum annealing (SSQA) for large-scale combinatorial optimization problems. SSQA is designed based on stochastic computing and qu…
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
Arash Ardakani, François Leduc-Primeau, Naoya Onizawa +2
The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware…
Associative Memories Based on Multiple-Valued Sparse Clustered Networks
Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu +1
Associative memories are structures that store data patterns and retrieve them given partial inputs. Sparse Clustered Networks (SCNs) are recently-introduced binary-weighted associ…
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks
Hooman Jarollahi, Naoya Onizawa, Warren J. Gross
Associative memories are structures that can retrieve previously stored information given a partial input pattern instead of an explicit address as in indexed memories. A few hardw…
A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa +1
A low-power Content-Addressable-Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The…