Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Abstract

Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA- SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems.

11 pages

References in corpus (9)

• Quantum annealing with more than one hundred qubits
• VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
• p-Bits for Probabilistic Spin Logic
• A Tutorial on Formulating and Using QUBO Models
• Optimized simulated annealing for Ising spin glasses
• Low Barrier Nanomagnets as p-bits for Spin Logic
• Efficient CMOS Invertible Logic Using Stochastic Computing
• Experimental quantum annealing: case study involving the graph isomorphism problem
• Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing

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• Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems
• Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture