15 citations · 34 across the 9 of their papers we have counts for
3 papers · 1 filter
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning
Nils Wistoff, Gernot Heiser, Luca Benini
Microarchitectural timing channels exploit information leakage between security domains that should be isolated, bypassing the operating system's security boundaries. These channel…
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor
Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi +6
Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardwar…
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
Luca Valente, Alessandro Nadalini, Asif Veeran +12
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) ucontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (na…