78 citations · 132 across the 8 of their papers we have counts for
9 papers
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
Matteo Perotti, Vincenzo Maisto, Moritz Imfeld +3
Vector processor architectures offer an efficient solution for accelerating data-parallel workloads (e.g., ML, AI), reducing instruction count, and enhancing processing efficiency.…
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
Enrico Zelioli, Alessandro Ottaviano, Robert Balas +3
The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands of modern autonomous systems require advanced heterogeneous embedded architectures. Such a…
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
Gianna Paulin, Paul Scheffler, Thomas Benz +11
We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit) SIMD FP data. Occamy…
Proving the Absence of Microarchitectural Timing Channels
Scott Buckley, Robert Sison, Nils Wistoff +4
Microarchitectural timing channels are a major threat to computer security. A set of OS mechanisms called time protection was recently proposed as a principled way of preventing in…
Towards a RISC-V Open Platform for Next-generation Automotive ECUs
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano +5
The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity po…
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Matteo Perotti, Matheus Cavalcante, Nils Wistoff +3
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips,…
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Michael Rogenmoser, Nils Wistoff, Pirmin Vogel +2
With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a ser…
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak +2
Microarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental security assumptions. They leverage timing variations of sever…
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak +2
Covert channels enable information leakage across security boundaries of the operating system. Microarchitectural covert channels exploit changes in execution timing resulting from…