15 citations · 34 across the 9 of their papers we have counts for
9 papers
CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems
Enrico Zelioli, Christopher Reinwardt, Nils Wistoff +4
This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implement…
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi +4
Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO…
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart +11
Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on t…
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
Thomas Benz, Paul Scheffler, Nils Wistoff +3
Open-source projects require outreach material to grow their community, secure funds, and strengthen their influence. Numbers, specifications, and facts alone are intangible to uni…
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
Paul Scheffler, Thomas Benz, Viviane Potocnik +12
ML and HPC applications increasingly combine dense and sparse memory access computations to maximize storage efficiency. However, existing CPUs and GPUs struggle to flexibly handle…
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning
Nils Wistoff, Gernot Heiser, Luca Benini
Microarchitectural timing channels exploit information leakage between security domains that should be isolated, bypassing the operating system's security boundaries. These channel…
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor
Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi +6
Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardwar…
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
Luca Valente, Alessandro Nadalini, Asif Veeran +12
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) ucontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (na…