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cs.AR2025
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
Dean You, Jieyu Jiang, Xiaoxuan Wang +9
Runahead execution is a technique to mask memory latency caused by irregular memory accesses. By pre-executing the application code during occurrences of long-latency operations an…
cs.AR2025
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
Tinglue Wang, Yiming Li, Wei Tang +6
Reliability and real-time responsiveness in safety-critical systems have traditionally been achieved using error detection mechanisms, such as LockStep, which require pre-configure…
cs.AR2025
NVR: Vector Runahead on NPUs for Sparse Memory Access
Hui Wang, Zhengpeng Zhao, Jing Wang +11
Deep Neural Networks are increasingly leveraging sparsity to reduce the scaling up of model parameter size. However, reducing wall-clock time through sparsity and pruning remains c…