10 citations · 29 across the 10 of their papers we have counts for
10 papers
GaloisSAT: Differentiable Boolean Satisfiability Solving via Finite Field Algebra
Curie Kim, Carsten Portner, Mingju Liu +6
Boolean satisfiability (SAT) problem, the first problem proven to be NP-complete, has become a fundamental challenge in computational complexity, with widespread applications in op…
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware
Minwoo Kang, Mingjie Liu, Ghaith Bany Hamad +2
The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital ch…
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
Mingjie Liu, Yun-Da Tsai, Wenfei Zhou +1
Despite the significant progress made in code generation with large language models, challenges persist, especially with hardware description languages such as Verilog. This paper…
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
Nathaniel Pinckney, Christopher Batten, Mingjie Liu +2
The application of large-language models (LLMs) to digital hardware code generation is an emerging field, with most LLMs primarily trained on natural language and software code. Ha…
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung Ho, Haoxing Ren, Brucek Khailany
Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and resul…
Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning
Yun-Da Tsai, Mingjie Liu, Haoxing Ren
Recent work targeting large language models (LLMs) for code generation demonstrated that increasing the amount of training data through synthetic code generation often leads to exc…
Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
Amit Sharma, Teodor-Dumitru Ene, Kishor Kunal +3
This paper presents a comparative analysis of total cost of ownership (TCO) and performance between domain-adapted large language models (LLM) and state-of-the-art (SoTA) LLMs , wi…
Large Language Model (LLM) for Standard Cell Layout Design Optimization
Chia-Tung Ho, Haoxing Ren
Standard cells are essential components of modern digital circuit designs. With process technologies advancing toward 2nm, more routability issues have arisen due to the decreasing…
ILILT: Implicit Learning of Inverse Lithography Technologies
Haoyu Yang, Haoxing Ren
Lithography, transferring chip design masks to the silicon wafer, is the most important phase in modern semiconductor manufacturing flow. Due to the limitations of lithography syst…
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
Yun-Da Tsai, Mingjie Liu, Haoxing Ren
This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities, ou…